This invention relates generally to obtaining a phase error of a clock signal-and, more particularly, to using that phase error to correct the phase of the clock signal.
Phase-locked loops (PLLs) operate in a control system, such as a disk drive, to synchronize the system and to reduce signal-to-noise (SNR) ratios in the system. In a disk drive, an analog signal is read from a storage medium, such as a computer hard disk, and is digitized using an analog-to-digital (A/D) converter. A clock signal clocks the A/D converter at specified points in the analog signal to produce the digital signal. If the clock signal is out of phase with the analog signal, noise may result in the digital signal.
A PLL is used to reduce phase errors between the analog signal and the clock signal. The PLL includes a phase detector, which detects phase errors in the digital signal. A filter filters these phase errors to obtain an overall phase error and controls the clock signal based on this overall phase error. Coefficients in the filter determine the amount of weight that individual phase errors are to be given in the filtering process.
In one aspect, the invention relates to obtaining a phase error of a clock signal. This aspect of the invention obtains a data signal based on the clock signal, determines the phase error of the clock signal based on the data signal, and corrects the phase error of the clock signal using information that is determined based on the data signal.
Among the advantages of this aspect of the invention may be one or more of the following. Information from the data signal, such as its slope, contains timing information that can be used to correct the phase error of the clock signal. For example, using the slope, it is possible to weight phase errors at particular points in the data signal, such as at data points, more heavily than phase errors at other points in the data signal. As a result, the corrected phase error can reflect a weighted average that reduces the effects of noise and the like in the phase error.
This aspect of the invention may include one or more of the following features and/or functions. The phase error is determined by obtaining an ideal waveform of the data signal and determining a difference in phase between the data signal and the ideal waveform. The information used in correcting the phase error includes coefficients which are determined based on the data signal.
The coefficients are determined by obtaining an ideal waveform of the data signal, calculating a slope of the ideal waveform, and determining the coefficients based on the slope of the ideal waveform. The coefficients are determined by determining an amplitude error of the ideal waveform, determining the phase error of the clock signal based on the slope and the amplitude error, and determining the coefficients based on the phase error.
The phase error of the clock signal is corrected using a proportional-integral filter having a first coefficient (xcex1) and a second coefficient (xcex2) that are determined using the data signal. The values for the first and second coefficients are determined based on a phase error and a frequency error associated with the data signal. The values for the first and second coefficients are determined using a covariance matrix that is based on the phase error and the frequency error.
The process for correcting the phase error includes reading data from a storage medium, processing the data, and sampling the processed data using the clock signal to obtain the data signal. The information used in correcting the phase angle error is obtained from a look-up table based on one or more values derived from the phase error.